IBM has unveiled a new chip architecture capable of integrating nearly 100 billion transistors onto a chip about the size of a human fingernail, according to reports. This is almost doubling the transistor density achieved by its previous-generation technology. The firm said the breakthrough could significantly boost computing performance and energy efficiency for AI data centers.
Jay Gambetta, IBM Fellow and Director of IBM Research, said that the innovation points to a future where computing power can increase substantially without a corresponding rise in energy consumption. Gambetta described it as a major advance rather than an incremental improvement.
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IBM has referred to the technology as the world's first "sub-1 nanometer chip technology". While it is untenable for chips with physical features smaller than one nanometer due to fundamental physical constraints, IBM's new "nanostack" architecture is designed to deliver performance and efficiency gains comparable to what could theoretically be expected from a sub-1 nanometer process node.
This "nanostack" architecture uses a vertically stacked, staggered transistor design to notably increase transistor density within the same chip footprint. The technology builds on the company's earlier work on nanosheet transistors, which formed the foundation of its 2-nanometer chip technology unveiled in 2021.
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By stacking transistors in multiple vertical layers rather than depending on horizontal scaling, IBM aims to deliver higher performance and improved energy efficiency which can service next-gen AI workloads.
The nanostack architecture could lay the groundwork for 50% higher computing performance or 70% more energy efficiency compared to company's previous generation of 2-nanometer node chips, as per projections from IBM's published technical reports.
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